Recently, according to tendency of the high-density of semiconductor memory devices into more than 16 Mbit, the size of a basic device, such as MOS transistor has been decreased to units of submicron.
Therefore, active and intensive research has been ongoing to improve the operating speed and the reliability of semiconductor memory devices according to reduced size of basic elements.
These high-density semiconductor memory devices comprise CMOS and NMOS circuits. Generally, semiconductor memory devices, for instance, DRAM devices include a data output buffer which has large current driving capability to increase fan-out of data output terminal connected thereto.
The data output buffer includes pull-up devices and pull-down devices connected in series between a supply voltage line and a ground line. The data output buffer applies supply voltage Vcc to a data output terminal connected to the node of the data output buffer through the pull-up device for outputting a high level of data output. And the data output buffer couples ground potential GND to a data output terminal connected to the node of the data output buffer through a pull-down device for outputting a low level of data output is outputted. However, in the case that the pull-up and pull-down devices constituting the data output buffer consist of NMOS transistors, a decreased voltage, which is decreased by threshold voltage VTN of NMOS transistor from the supply voltage Vcc when the data of "HIGH" is outputted, is applied to a data output terminal with the result that operation margin of a high level of data is reduced and the operating speed becomes slow.
Also in the case that the pull-up and pull-down devices constituting the data output buffer consist of CMOS transistors, the high level of data of vcc and improved operating speed can be obtained. However, it still has disadvantages of latch-up which peculiarly results from the CMOS circuit.
To obviate the above disadvantages, a bootstrap circuit is incorporated into a data output buffer made of NMOS transistors, in which a pull-up device is driven by a boosted voltage, so that a high level of data is outputted as a supply voltage level. Although the data output buffer comprising the bootstrap circuit can achieve the improved operation margin and the operating speed in a low level of supply voltage, it has the following disadvantage in the state transition of data in a high level of supply voltage.
That is, undesirable ringing occurs due to greater overdrive, which gives rise to secondary overshoot exceeding the maximum low level output voltage VOL max.
Such secondary overshoot causes reduction of a low level noise margin NML and simultaneously delays an arrival time of the stable low level output, with the result that the access time is lengthened. At this time, low level noise margin NML is determined by the difference between the maximum low level input voltage VIL max of the device to be driven and the maximum low level output voltage of the driving device VOL max.
In the circuit of FIG. 1 which is also illustrated in Korean Patent Application No. 89-11995 filed by the same applicant, a voltage of a node A is pumping at Vcc-VTN during the first read-cycle in an enable-state of a semiconductor memory chip. Therefore, an access time of a high logic data becomes long because the pumping level is low.
To raise the pumping level, if the size of a pumping capacitor C.sub.1 is made to increase, the reduction of the operating speed can be prevented at Vcc of the low level but noises of a supply voltage and ground line occur at the supply voltage Vcc of the high level. Also, in case of a high level Vcc in the small size of a pumping capacitor C.sub.1, since an invalid "HIGH" level of voltage is high level, the noise of the ground line occurs by the undershoot during the valid falling transition.
Referring to the circuit of FIG. 2, by making the voltage of node A full Vcc through the initial pumping circuit 3, the boosting voltage level during the first read cycle is high although the same pumping capacitor is of the same size as that of FIG. 1. However, the noise of supply voltage line due to an invalid "High" at a high level Vcc is also large.
To reduce this noise, it is required that the size of pull-down transistor be reduced or the rising transition of the gating signal smooth, which inevitably leads to a slow operating speed.
To eliminate above disadvantages, Korean Patent Application No. 89-11995 disclosed a circuit as shown in FIG. 3, which circuit further comprises as auxiliary means, a pumping capacitor C.sub.3 and a pull-down transistor M6. Below a predetermined supply voltage level, the operating speed is improved by operating the auxiliary means, also above the predetermined supply voltage level having the problem of the noises of supply line and ground line, the line noise is greatly reduced by not operating the auxiliary means.
However, since the circuit of FIG. 3 should include extra pumping capacitor C3, pull-down transistor M6 and control the means NO1, NO2 to control above devices, a circuit configuration is complicated and more chip area is occupied, thereby preventing high-density integration.